SBF50F series is a System-On-Chip integrated 2.4GHz radio transceiver and baseband processor for Bluetooth Low Energy 5(BLE 5). It contains the high-performance ARM® CortexTM-M0 32-bit RISC core, 256KB embedded Flash, 512KB embedded SRAM, the hardware of Link Layer for BLE 5, 2.4GHz radio transceiver and peripheral for application.
■ Key Features
- Processor
– ARM® CortexTM-M0 CPU speed up to 66.5MHz
– Single-cycle hardware multiplier
– 24-bits SysTick timer
- NVIC
– Supports up to 32 discrete interrupts
– 4 levels of priorities
– Both level-sensitive and edge-sensitive interrupts can be handled
- Embedded Flash Memory
– 256 KB of Flash memory
– In-system self-programmable
– programmable by SWD or proprietary protocol
- SRAM Memory
– 51 KB embedded SRAM
- Reset
– Power-on reset (POR)
– External reset pin
– Watchdog timer time-out reset
- Clock
– 26 MHz external crystal oscillator
– 32.768 KHz external crystal oscillator
– Up to 133 MHz DPLL
– Internal 32.768 KHz on-chip oscillator
- Low power modes
– Sleep mode
– Deep-sleep mode
– Power standby mode
– SPU sleep mode
– SPU deep-sleep mode
– SPU power down mode
– SPU deep power down mode
- Peripherals
– GPIO
◆ 31 programmable I/O pins
◆ Configurable pull-up or pull-down
◆ Selectable output driving capability: 2mA or 4mA/4mA or 15MA
– Timers
◆ Two 32-bit timers: Timer0 and Timer1
◆ Independent clock source for each timer
– Dual Timer
◆ Two programmable 32-bit or 16-bit timers
◆ Three kinds of timer modes:
• Free-running
• Periodic
• One-shot
– Watchdog Timer
◆ Multiple clock sources
◆ Configurable interrupt or reset output on watchdog time-out
– PWM
◆ Up to 8 channel PWM output
◆ Configurable clock pre-scalar for the counters
◆ Selectable PWM output pin location and polarity for each channel
– CRC32
◆ 32bit cyclic redundancy check algorithm using the generator polynomial 0x04C11DB7
– RTC
◆ Supports calendar, time and alarm
◆ Leap year compensation
◆ Supports periodic interrupt with 4 period options: second/minute/hour/day
◆ Supports System wake up from low power mode
– UART
◆ Support serial frames with 8 data bit and 1 stop bit
◆ Does not support parity bit checking
– SPI
◆ Support master and slave mode
◆ Configurable SPI clock speed: 1/2 to 1/512 of the system clock
◆ Supports various character data format: 8 to 32 bits
◆ Supports different CPOL and CPHA settings
◆ Configurable delay cycles for receive data under master mode
– I2C
◆ Compatible to I2C specification
◆ Programmable clock rate, supports 100KHz
◆ Supports 7 bits and 10 bits addressing mode
◆ Only support master mode
– QDEC
◆ Three axes supported
◆ Configurable of sample and report period
◆ Optional input de-bounces filters
◆ Optional LED output signal
◆ Programmable source from all GPIOs
– QSPI
◆ Supports CPU direct read from AHB Bus
◆ Support 2 KB cache memory for CPU direct read
◆ Support single, dual and quad I/O interface
◆ Programmable clock frequency and clock source
◆ Programmable receive clock delay cycle for high speed access
◆ Programmable dummy cycles
◆ Supports address 3 bytes or 4 bytes
– ADC
◆ 12-bit resolution
◆ 8 analog input channels(2 sets, 4 channels for each set)
◆ 2 operation modes:
• Single mode: single-channel or different-channel, single conversion
• Scan mode: continuous conversions on selected channels
– Temperature sensor
◆ Support threshold detection
◆ Support temperature measure
- Power
– Programmable TX output power: -20dBm ~+10dBm in 4dB sets
– Rx sensitivity
◆ 2M(2Mdps): -93dBm
◆ 1M(1Mdps): -95dBm
◆ S2(500Kdps): -97dBm
◆ S8(125Kdps): -100dBm
– SPU deep power down mode: under 1uA
– Buck DC-DC convertor.
◆ Input: VBAT = 2.5V~4.4V
◆ Output: VOUT = 1.55V~2.75V
– Core LDO for system power.
◆ Input: VCC = 1.8V~3.6V
◆ Output: VDD = 1.2V
■ Application
| Bluetooth beacon Health & Fitness sensors Remote Controls Connected Medical sensors |
Fitness trackers/Smart watches Wireless PC peripherals Smart Home automation |
